Senior Digital IC Design and Verification Engineer

Our customer isrn a leading telecom solutions provider. Through continuous customer-centricrn innovation, our customer has established end-to-end advantages in Telecomrn Network Infrastructure, Application & Software, Professional Services andrn Devices. With comprehensive strengths in wireline, wireless and IPrn technologies, our customer has gained a leading position in the All-IPrn convergence age. Its products and solutions have been deployed in over 100rn countries and have served 45 of the world's top 50 telecom operators, as wellrn as one third of the world's population.

Their R&D teamsrn develop next generation RF transceivers, supporting 4G (LTE) and 5G systems.

The Senior Digital Design & Verificationrn Engineer has the following responsibilities:

• Integrate legacy control and data path designs in new products.


• Update and verify legacy designs to fit new product requirements.


• Design and verify new ultra-high speed DSP blocks for next gen products.


• Interface with the physical implementation team for furtherrn design and flow improvements.

This role includes technical leadership, meaningrn technical hands-on expertise and excellent team skills; this candidatern targets high and challenging standards on technical performance, product andrn process quality and project schedule.

Location:rn Leuven

Candidate Description

·        rn MSEE or equivalentrn with min 3 to 5y industrial experience

·        rn Solid grasp ofrn simulation concepts such as regression testing, UVM, functional coverage,rn assertions, …

·        rn Good knowledge ofrn Verilog and SystemVerilog for design and verification

·        rn Experience withrn RTL lint

·        rn Knowledgeablern about DFT and ATPG

·        rn Knowledgeablern about CDC issues and techniques for low power design

·        rn Experience withrn delay annotated gatelevel simulation

·        rn Experience withrn implementation of high-speed pipelined FIR DSP structures is a plus

·        rn Formalrn Verification experience is a plus

·        rn Formal lint

·        rn Sequentialrn Equivalence Checking

·        rn Assertion Basedrn Verification

·        rn Experience withrn C/C++/SystemC models for RTL verification a must

·        rn Python and TCLrn programming experience a strong plus

·        rn Able torn efficiently work in a Linux command line environment as well as in Windows MSrn Office for reporting and documentation

·        rn Excellentrn analytical skills

·        rn Good communicationrn skills

·        rn Team-player

·        rn Result driven

·        rn Continuous strivern for improvement in circuits and process

·        rn Detail orientedrn and determined

·        rn Willing torn relocate to Leuven (Belgium) region